Career Profile
Muhammad Aslam received the B.Sc. degree in electronics engineering from International Islamic University, Islamabad, Pakistan, in 2014, the M.S. degree in electronics and telecommunication engineering from the University of Kocaeli, Turkey, in 2017, and the P.hD. degree in electrical engineering from the Ghent University, Belgium, in 2022. He has worked as Design and Verification Engineer at Yonga Technology Microelectronics, Turkey for more than one year. Apart from that, he has worked as a researcher at IDLab – an imec research group at Ghent University – for five years. Currently, he has been working as a senior FPGA engineer at ST Engineering iDirect. His current research/industrial interests include wireless communication standards (IEEE 802.15.4, IEEE 802.11, NTN), wireless time-sensitive networking, video coding/motion estimation and their real-time implementation on SoC platforms.
Education
PhD Thesis
Hardware Efficient Designs for Deterministic and Low Latency Wireless Communication System Using Software-Define Radio.
Master Thesis
Low bit-depth based Motion Estimation (ME) and its Hardware Architecture for H.264 and HEVC. The proposed hardware architecture of ME can process 93 1280×720 full HD frames per second with only 25 milliwatts of power consumption for H.264 and can process up to 52 720p full HD frames per second with 284.9mW average power consumption for H.265.
Final Year Project
Soft Multi-rate Viterbi Decoder Implementation On Matlab and FPGA(Sparten3E). The Decoder supports constraint lengths of 3, 4, 7, and code rates of 1/2, 2/3,3/4.
Experiences
My contributions during the role includes: (1). Involvded in designing and implementing NTN return technology.More details?
My contributions during the role includes: (1). Impelementation of IEEE 802.15.4 standard compliant SDR with full communication stack, supporting flexible data rate ranging from 31.25kbps to 2Mbps and tunable RF frequency ranging from 70 MHz to 6 GHz.More details? (2). Impelementation of IEEE 802.15.4 compliant multi-channel virtual transceiver, capable of transmit/receive data on up-to 8 radio channels simultaneously. More details? (3) .Implementation of 802.11ax extension for openwifi (in progress).More details?
My contributions during the role includes: (1). Develop Zynq architecture based Testing Environment which consists of AXI stream based IP, DMA IP, DDR RAM, UART and Ethernet interface. (2). RTL based design for H.264 video encoder, To this end, H.264 video encoder (profile: BASELINE, Level:3.1) was first simulated in MATLAB and then designed in FPGA. The encoder was tested on CYCLONE-V FPGA connected with PC via Ethernet. The encoded bitstream of our encoder was decoded by the VLC media player, running on PC in real time.